Flash memory device capable of reduced programming time

ABSTRACT

A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls the word line voltage generator circuit so that either the unit program time or the increment size of the word line voltage is varied according to the number of program data bits among the set of input data bits that the device will store in memory cells.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a semiconductor memory device, and,in particular, a NOR flash memory device.

This application claims the benefit of Korean Patent Application No.2004-105622, filed Dec. 14, 2004, the disclosure of which is herebyincorporated by reference in its entirety.

2. Description of Related Art

Semiconductor memory devices are a vital microelectronic componentcommonly found in digital logic systems, such as computers, andmicroprocessor-based applications ranging from satellites to consumerelectronics. Therefore, advances in the fabrication of semiconductormemory devices, including process enhancements andcircuit-design-related developments that allow scaling to higher memorydensities and faster operating speeds, help establish performancestandards for other digital logic families. Semiconductor memory devicesgenerally include volatile memory devices, such as random access memory(RAM) devices, and nonvolatile memory devices. In RAM devices, data isstored by either establishing the logic state of a bistable flip-flopsuch as in a static random access memory (SRAM), or by charging acapacitor in a dynamic random access memory (DRAM). In both SRAM andDRAM devices, data remains stored and may be read as long as the poweris applied, but data is lost when the power is turned off.

In contrast, nonvolatile memories are capable of storing data even whenthe power is turned off. Nonvolatile memory data storage modes includepermanent and reprogrammable modes. Nonvolatile memories are commonlyused for program and microcode storage in a wide variety of applicationsincluding computers, avionics, telecommunications, and consumerelectronics. A combination of volatile and nonvolatile memory devicesand related storage modes are available in devices such as nonvolatileSRAM (nvRAM) devices. These devices are used, for example, in systemsthat require fast, reprogrammable nonvolatile memory.

Mask read-only memory (MROM), programmable read-only memory (PROM) anderasable programmable read-only memory (EPROM) nonvolatile memorydevices are not readily writeable or erasable, so it is not easy toupdate the contents of the memory. On the other hand, electricallyerasable programmable read-only memory (EEPROM) nonvolatile memorydevices are electrically erasable and writable, and may, thus, bereadily applied to auxiliary memories or system programming memoriesthat require continuous update.

Flash memory, which is a type of EEPROM, is one example of a nonvolatilememory device. While standard EEPROM can only erase or write one byte ofdata in a single programming operation, flash memory can erase or writemultiple bytes, or “blocks”, of data in a single programming operation.

Flash memory devices store data on a silicon chip in such a way thateven if the power to the chip is turned off, the data is retained on thechip. The two general types of flash memory are NOR flash memory andNAND flash memory. NOR flash memory uses a NOR logic gate in each cellwhile NAND flash memory uses a NAND logic gate in each cell. In flashmemory devices, each cell can typically store one bit of data, thoughthere are also multi-bit flash memory devices in which each cell canstore two or more bits of data. In flash memory devices, cells arearranged in rows and columns to form an array of cells.

The following is an exemplary configuration of a flash memory cell. In aflash memory cell, a bit line and a word line are connected to the cell,which comprises a control gate, a floating gate, a substrate with asource and a drain, and two oxide layers. The cell is arranged so thatthe word line is connected to the control gate, and the bit line isconnected to the substrate, with the floating gate between the controlgate and the substrate. Between the control gate and the floating gateis the first oxide layer, and between the floating gate and thesubstrate is the second oxide layer.

The data state of the cell is determined by the threshold voltage of thecell. A cell having a low threshold voltage corresponds to the datastate “1”, or “erased”, for the data bit held in the cell, and a highthreshold voltage corresponds to the data state “0”, or “programmed”,for the data bit held in the cell. The cell is brought from the erasedstate to the programmed state using a process called Fowler-Nordheimtunneling. To program the cell using Fowler-Nordheim tunneling, the wordline supplies the control gate with a high voltage, while the bit linesupplies the substrate with a low voltage, creating a voltage differencebetween the control gate and the substrate strong enough to pullelectrons out of the substrate towards the floating gate. The electronsare then trapped between the control gate and the first oxide layercreating a barrier between the control gate and the floating gate andraising the threshold voltage of the cell to a value associated with theprogrammed state. Cells can typically be programmed by the byte or bythe word.

To erase the cell, the bit line supplies a high voltage to the substrateand the word line supplies a low voltage to the control gate causing avoltage difference between the control gate and the substrate thatcauses the trapped electrons to be pulled back across the first oxidelayer and into the substrate, removing the barrier that the electronsformed and reducing the threshold voltage of the cell to a valueassociated with the erased state. Cells cannot be erased individually,but rather the cells are erased by the block.

To read the state of the cell, a voltage is applied to the control gateand the cell will either provide a relatively high voltage to the bitline, which the flash memory device reads as the cell having aprogrammed state, or a relatively low voltage, which the flash memorydevice reads as the cell having an erased state.

NOR flash memory devices perform programming operations within programloops, each of which consists of a program interval and a program verifyinterval. In each program loop, the device programs memory cells duringthe program interval and checks whether or not memory cells areprogrammed during the program verify interval. A time period(hereinafter, referred to as “programming time”) of sufficient durationto execute each program interval is provided during each program loop.Programming time is defined as the time required to program memory cellsas described above when each bit in the set of input data bits has alogical value “0”. The voltage level applied to a bit line is a criticalconsideration in the determination of programming time. Thisconsideration arises from the fact that the applied bit line voltage isgenerally lower than a defined threshold voltage during this period ofprogramming operations. Hence, the programming time of each program loopis set to the maximum programming time required to program the memorycells, under the condition that each bit in the set of input data bitshas a logical value “0”. Hereinafter, a data bit having a logical value“0” is called a “program data bit” and a data bit having a logical value“1” is called a “program-inhibit data bit”.

Conventionally, a programming time has been determined by the abovecondition and used for all inputs, even when some of the input bits inthe input are program-inhibit data bits rather than program data bits.Maintaining a constant programming time regardless of the number ofprogram data bits actually apparent in the input data slows theperformance of the NOR flash memory device.

Accordingly, a technique capable of improving the programmingperformance of the NOR flash memory device is required.

SUMMARY OF THE INVENTION

In one embodiment, the invention provides a flash memory devicecomprising word line voltage generator circuit configured to generate aword line voltage, wherein the word line voltage is varied in accordancewith an increment size, and a program controller circuit adapted tocontrol the word line voltage generator circuit and further adapted todefine the increment size in accordance with a number of program databits in a set of input data bits.

In another embodiment, the invention provides a flash memory devicecomprising a word line voltage generator circuit configured to generatea word line voltage, wherein the word line voltage is varied inaccordance with an increment size, and a program controller circuitadapted to control the word line voltage generator circuit and furtheradapted to define a unit program time for the word line voltage inaccordance with a number of program data bits in a set of input databits.

In yet another embodiment, the invention provides, a method forcontrolling a flash memory device is provided which comprises generatinga word line voltage, wherein the word line voltage is varied inaccordance with an increment size, and defining the increment size inaccordance with a number of program data bits in a set of input databits.

In still another embodiment, the invention provides a method forcontrolling a flash memory device is provided which comprises generatinga word line voltage, wherein the word line voltage is varied inaccordance with an increment size, and defining a unit program time inaccordance with a number of program data bits in a set of input databits.

BRIEF DESCRIPTION OF THE DRAWINGS

An appreciation of the present invention, and many of its attendantadvantages, will become readily apparent upon consideration ofembodiments of the invention with reference to the accompanying drawingsin which like reference symbols indicate the same or similar components,wherein:

FIG. 1 shows a block diagram of a NOR flash memory device according toone embodiment of the present invention;

FIGS. 2A to 2C show word line voltage increment size variations for aprogramming operation of a NOR flash memory device in FIG. 1;

FIGS. 3A to 3C show variations in the unit program time for aprogramming operation of a NOR flash memory device in FIG. 1; and

FIG. 4 shows a block diagram of a NOR flash memory device according toanother embodiment of the present invention.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 1 is a block diagram showing a nonvolatile memory device accordingto one embodiment of the invention. A NOR flash memory device isillustrated in FIG. 1. However, those of ordinary skill in the art willunderstand that the invention may be applied to other types of memorydevices such as MROM, PROM, ferroelectric random access memory (FRAM), aNAND flash memory device, etc.

Referring to FIG. 1, a NOR flash memory device 100 is shown andgenerally includes a memory cell array 110 comprising nonvolatile memorycells arranged in an array of word lines (or rows) and bit lines (orcolumns). A row selector circuit 120 selects at least one of the wordlines in response to a row address RA and supplies a word line voltageVWL to the selected word line. A word line voltage generator circuit 130is controlled by a program controller circuit 200 and generates the wordline voltage VWL to be supplied to the selected word line. In theillustrated example, word line voltage generator circuit 130 isconfigured to generate the word line voltage VWL using incremental steppulse programming (ISPP) within the overall programming operation. InISPP, the word line voltage VWL is increased stepwise from a minimumvoltage (for example, 2V) to a maximum voltage (for example, 9V) withinthe program interval of each program loop. Program controller circuit200 may vary the increment size for the word line voltage VWL inaccordance with the number of program data bits in a set of input databits. Alternatively, the program controller circuit 200 may vary theunit program time in accordance with the number of program data bits inthe set of input data bits. Herein, the unit program time is a timewithin a program interval where the level of word line voltage VWL ismaintained, and between which the word line voltage is incremented.

A column selector circuit 140 selects bit lines of memory cell array 110according to a defined unit size (for example, ×8, ×16, ×32, etc.) inresponse to a column address CA. During a programming operation, a writedriver circuit 150 temporarily stores data values transferred via a datainput circuit 160 and drives bit lines, which are selected by columnselector circuit 140, with a bit line voltage in accordance with thestored data values. During a read/verify operation, a sense amplifiercircuit 170 senses and amplifies the logic states, either programmed orerased, of memory cells via bit lines selected by column selectorcircuit 140. During the verify operation, a pass/fail check circuit 180outputs a judgment result to program controller circuit 200 in responseto the states of the memory cells sensed by pass/fail check circuit 180.The sensed state for each one of the memory cells is provided to writedriver circuit 150, so that programmed memory cells may beprogram-inhibited, if desired.

For example, assume that the data value to be programmed in a memorycell is “0”. If the sensed state of the memory cell is “1” indicating anerased state, the data value temporarily stored in write driver circuit150 for the memory cell is maintained at “0”. This means that the memorycell must be programmed within the next program loop. That is, a bitline voltage is supplied to the bit line which is connected to thememory cell to be programmed.

If, however, the sensed state of the memory cell is “0” indicating aprogrammed state, the data value temporarily stored in write drivercircuit 150 for the memory cell is changed from “0” to “1”. This meansthat the memory cell must be program-inhibited within the next programloop.

During the programming operation, data input circuit 160 provides bothwrite driver circuit 150 and bit counter circuit 190 with the set ofinput data bits. Bit counter circuit 190 counts (or calculates) thenumber of program data bits in the set of input data bits. Bit countercircuit 190 then provides program controller circuit 200 with the numberof counted program data bits. Program controller circuit 200 isconfigured to control overall operation of the program loops. Programcontroller circuit 200 controls word line voltage generator circuit 130so that the word line voltage VWL increment size is maintained at areference value or increased above the reference value in accordancewith the number of program data bits determined by bit counter circuit190. Alternatively, program controller circuit 200 controls word linevoltage generator circuit 130 so that the unit program time ismaintained at the reference value or decreased below the reference valuein accordance with the number of program data bits determined by bitcounter circuit 190.

In one embodiment of the invention, the foregoing reference value forvoltage is a voltage that corresponds to a voltage required when the setof input data bits contains all program data bits, and the foregoingreference value for unit program time is a time that corresponds to theunit program time required when the set of input data bits contains allprogram data bits.

FIGS. 2A through 2C are voltage diagrams showing exemplary word linevoltage variations for defining a programming operation of a NOR flashmemory device like the one shown in FIG. 1. For example, prior to theexemplary programming operations shown in FIGS. 2A through 2C, it isassumed that the exemplary NOR flash memory device 100 shown in FIG. 1has been configured to variously control the increment size of a wordline voltage VWL according to whether a number of program data bits isgreater than 8, whether it is less than or equal to 8 but greater than4, or whether it is less than or equal to 4. These definitions are justselected examples, and those of ordinary skill in the art willunderstand that any reasonable definition is possible.

Once NOR flash memory device 100 enters a programming mode of operation,data input circuit 160 inputs a data word comprising the set of inputdata bits. Since NOR flash memory device 100 will be programmed inrelation to this data word it is temporarily stored in write drivercircuit 150. Bit counter circuit 190 calculates the number of programdata bits from the set of input data bits. If the calculated number ofprogram data bits is greater than 8, as illustrated in FIG. 2A, programcontroller circuit 200 controls word line voltage generator circuit 130so that it increases the word line voltage VWL stepwise by an incrementsize (ΔV) of 0.5V. If the calculated number of program data bits is lessthan or equal to 8 but greater than 4, as illustrated in FIG. 2B,program controller circuit 200 controls word line voltage generatorcircuit 130 so that it increases the word line voltage VWL stepwise byan increment size (ΔV) of 1.0V. If the calculated number of program databits is less than or equal to 4, as illustrated in FIG. 2C, programcontroller circuit 200 controls word line voltage generator circuit 130so that it increases the word line voltage VWL stepwise by an incrementsize (ΔV) of 2.0V. Thus, illustrated in FIGS. 2A through 2C, theincrement size of the word line voltage VWL is varied in accordance withthe number of program data bits while the unit program time (t) is heldconstant.

The word line voltage VWL generated by word line voltage generatorcircuit 130 supplied to a word line selected by row selector circuit120. Write driver circuit 150 drives bit lines selected by columnselector circuit 140 with a bit line voltage, defined in relation to theset of input data bit values. As described above, in the case where theinput data bit is a program data bit, a bit line voltage is supplied toa bit line. On the other hand, if the input data bit is aprogram-inhibit data bit, no bit line voltage is supplied to a bit line.Once a word line voltage VWL is supplied to a selected word line and abit line voltage is supplied to a selected bit line, the flash memorydevice starts to program a memory cell as described above. When theprogram interval of a program loop has ended, program controller circuit200 detects whether threshold voltages of programmed memory cells havebeen properly shifted to the desired threshold voltage. This isaccomplished using sense amplifier circuit 170 and pass/fail checkcircuit 180 in a conventional manner.

If the flash memory device determines that the threshold voltages ofprogrammed memory cells have been properly shifted to the desiredthreshold voltage, then the flash memory device determines that thecurrent program loop is successful, e.g., “program pass”, and theprogram mode of operation ends. On the other hand, if the flash memorydevice determines that the threshold voltages of programmed memory cellshave not been properly shifted to the desired threshold voltage, thenthe flash memory device determines that the current program loop is notsuccessful, e.g., “program fail”, and program controller circuit 200performs a repeated program loop, which is another programming operationexecuted under the same configuration using, for example, one of theconfigurations described in relation to FIGS. 2A to 2C to essentiallyrepeat the program loop.

So, in the flash memory device according to one embodiment of theinvention, an initially determined configuration is maintained until theprogram mode of operation is ended, and thus, repeated program loops maybe executed with the same voltage increment size established in theinitial program loop.

In the foregoing embodiment, bit counter circuit 190 and programcontroller circuit 200 constitute a word line voltage controllercircuit, of sorts, configured to control the word line voltage generatorcircuit to vary the increment size of the word line voltage or the unitprogram time in accordance with the number of program data bits in a setof input data bits to be stored in selected memory cells.

As set forth above, when each bit in the set of input data bits is aprogram data bit, the word line voltage increment size is set at aminimum value. However, it is possible to increase the voltage incrementsize when there are fewer program data bits in the set of input databits. For example, when performing a programming operation according tothe configuration described in relation to FIG. 2A, which is defined inthe illustrated example according to a number of program data bitsgreater than 8, the programming time for each program loop is set at,for example, 16 t. As another example, when performing a programmingoperation according to the configuration described in relation to FIG.2B, which is defined in the illustrated example according to a number ofprogram data bits less than or equal to 8 but greater than 4, theprogramming time for each program loop is set at, for example, 8 t. Asstill another example, when performing a programming operation accordingto the configuration in relation to FIG. 2C, which is defined in theillustrated example according to a number of program data bits less thanor equal to 4, the programming time of each program loop is set at, forexample, 4 t. Thus, it is possible to reduce the programming time foreach program loop (or an overall programming time) based on the numberof program data bits apparent in a set of input data bits by variablycontrolling the increment size of the word line voltage VWL accordingly.

FIGS. 3A through 3C are voltage diagrams showing exemplary unit programtime variations for defining a programming operation of a NOR flashmemory device like the one shown in FIG. 1.

For example, prior to describing the exemplary programming operationsshown in FIGS. 2A through 2C, it is assumed that the exemplary NOR flashmemory device 100 shown in FIG. 1 has been configured to variouslycontrol the unit program time according to whether a number of programdata bits is greater than 8, whether it is less than or equal to 8 butgreater than 4, or whether it is less than or equal to 4. Thesedefinitions are just selected examples, and those of ordinary skill inthe art will understand that any reasonable definition is possible.

Once NOR flash memory device 100 enters a programming mode of operation,data input circuit 160 inputs a data word comprising the set of inputdata bits. Since NOR flash memory device 100 will be programmed inrelation to this data word it is temporarily stored in write drivercircuit 150. Bit counter circuit 190 calculates the number of programdata bits in the set of input data bits. If the calculated number ofprogram data bits is greater than 8, as illustrated in FIG. 3A, programcontroller circuit 200 controls word line voltage generator circuit 130so that the unit program time is set to a time (t) during the programinterval. If the calculated number of program data bits is less than orequal to 8 but greater than 4, as illustrated in FIG. 3B, programcontroller circuit 200 controls word line voltage generator circuit 130so that the unit program time during the program interval is set to atime (t′) that is shorter than the time (t) (t>t′). If the calculatednumber of program data bits is less than or equal to 4, as illustratedin FIG. 3C, program controller circuit 200 controls the word linevoltage generator circuit 130 so that the unit program time during theprogram interval is set to a time (t″) that is shorter than the time(t′) (t>t′>t″). Thus, as illustrated in FIGS. 3A through 3C, the unitprogram time is varied in accordance with the number of program databits while the increment size (ΔV) of the word line voltage VWL heldconstant.

The word line voltage VWL generated by word line voltage generatorcircuit 130 is supplied to a word line selected by row selector circuit120. Write driver circuit 150 drives bit lines selected by the columnselector circuit 140 with a bit line voltage, defined in relation toinput data states. As described above, in the case where an input databit is a program data bit, a bit line voltage is supplied to a bit line.On the other hand, if an input data bit is a program-inhibit data bit,no bit line voltage is supplied to a bit line. Once a word line voltageVWL is supplied to a selected word line and a bit line voltage issupplied to a selected bit line, the flash memory device starts toprogram a memory cell. When the program interval of a program loop hasended, program controller circuit 200 detects whether threshold voltagesof programmed memory cells have been properly shifted to the desiredthreshold voltage. This is accomplished using sense amplifier circuit170 and pass/fail check circuit 180 in a conventional manner.

If the flash memory device determines that the threshold voltages ofprogrammed memory cells have been properly shifted to the desiredthreshold voltage, then the flash memory device determines that thecurrent program loop is successful, e.g., “program pass”, and theprogram mode of operation ends. On the other hand, if the flash memorydevice determines that the threshold voltages of programmed memory cellshave not been properly shifted to the desired threshold voltage, thenthe flash memory device determines that the current program loop is notsuccessful, e.g., “program fail”, and program controller circuit 200executes another programming operation under the same configurationusing, for example, one of the configurations described in relation toFIGS. 3A to 3C to essentially repeat the program loop.

So, in the flash memory device according to one embodiment of theinvention, an initially determined configuration is maintained until theprogram mode of operation is ended, and thus, repeated program loops maybe performed with the same unit program time established in the initialprogram loop.

As set forth above, when each bit in the set of input data bits is aprogram data bit, the length of the unit program time is set at amaximum value. However, it is possible to shorten the unit program timewhen there are fewer program data bits in the set of input data bits.For example, when performing a programming operation according to theconfiguration described in relation to FIG. 3A, which is defined in theillustrated example according to a number of program data bits greaterthan 8, the programming time for each program loop is set at, forexample, 16 t. As another example, when performing a programmingoperation according to the configuration described in relation to FIG.3B, which is defined in the illustrated example according to a number ofprogram data bits less than or equal to 8 but greater than 4, theprogramming time of each program loop is set at, for example, 16 t′(t>t′). As still another example, when performing a programmingoperation according to the configuration described in relation to FIG.3C, which is defined in the illustrated example according to a number ofprogram data bits less than or equal to 4, the programming time of eachprogram loop is set at, for example, 16 t″ (t>t′>t″). Thus, it ispossible to reduce the programming time for each program loop (or anoverall programming time) based on the number of program data bitsapparent in a set of input data bits by variably controlling the unitprogram accordingly.

FIG. 4 is a block diagram showing a nonvolatile memory device accordingto another embodiment of the invention. Referring to FIG. 4, a NOR flashmemory device 300 is shown and generally includes a memory cell array310 comprising nonvolatile memory cells arranged in an array of wordlines (or rows) and bit lines (or columns). A row selector circuit 320selects at least one of the word lines in response to a row address RAand supplies a word line voltage VWL to the selected word line. A wordline voltage generator circuit 330 is controlled by a program controllercircuit 400 and generates the word line voltage VWL to be supplied tothe selected word line. In the illustrated example, word line voltagegenerator circuit 330 is configured to generate the word line voltageVWL using incremental step pulse programming (ISPP) within the overallprogramming operation. Program controller circuit 400 controls theincrement size for the word line voltage VWL, which may be varied inaccordance with the number of program data bits that bit counter circuit390 counts. Alternatively, program controller circuit 400 controls theunit program time, which may be varied in accordance with the number ofprogram data bits that bit counter circuit 390 counts.

A column selector circuit 340 selects bit lines of memory cell array 310according to a defined unit size (for example, ×8, ×16, ×32, etc.) inresponse to a column address CA. During a programming operation, a writedriver circuit 350 temporarily stores the data states transferred viathe data input circuit 360 and drives bit lines, which are selected bycolumn selector circuit 340, with a bit line voltage in accordance withthe stored data states. During a read/verify operation, a senseamplifier circuit 370 senses and amplifies the logic states, eitherprogrammed or erased, of memory cells via bit lines selected by columnselector circuit 340. During the verify operation, a pass/fail checkcircuit 380 outputs a judgment result to program controller circuit 400in response to the states of the memory cells sensed by pass/fail checkcircuit 380. The sensed state for each one of the memory cells isprovided to write driver circuit 350, so that programmed memory cellsmay be program-inhibited, if desired.

For example, assume that a data value to be programmed in a memory cellis “0”. If the sensed state of the memory cell is “1” indicating anerased state, the data value temporarily stored in write driver circuit350 for the memory cell is maintained at “0”. This means that the memorycell must be programmed within the next program loop. That is, a bitline voltage is supplied to the bit line which is connected to thememory cell to be programmed.

If, however, the sensed state of the memory cell is “0” indicating aprogrammed state, the data value temporarily stored in write drivercircuit 350 for the memory cell is changed from “0” to “1”. This meansthat the memory cell must be program-inhibited within the next programloop.

During the programming operation, data input circuit 360 provides bothwrite driver circuit 350 and bit counter circuit 390 with the datainput. Bit counter circuit 390 counts (or calculates) the number ofprogram data bits from the set of input data bits. Bit counter circuit390 then provides program controller circuit 400 with the number ofcounted program data bits. Program controller circuit 400 is configuredto control overall operation of the program loops. Program controllercircuit 400 controls word line voltage generator circuit 330 so that theword line voltage VWL increment size is maintained at a reference valueor increased above the reference value in accordance with the number ofprogram data bits determined by bit counter circuit 390. Alternatively,program controller circuit 400 controls word line voltage generatorcircuit 330 so that the unit program time is maintained at the referencevalue or decreased below the reference value in accordance with thenumber of program data bits determined by bit counter circuit 390.

Program controller circuit 400 also controls bit counter circuit 390during a program verify operation. Bit counter circuit 390 receivessensed data states from pass/fail check circuit 380 and calculates thenumber of program data bits in the sensed data states and providescontroller circuit 400 with the number of counted program data bits.

Program controller circuit 400 controls word line voltage generatorcircuit 300 so that the word line voltage VWL increment size ismaintained at a reference value or increased above the reference valuein accordance with the number of program data bits counted by bitcounter circuit 390 at each program loop, including repeated programloops. Alternatively, program controller circuit 400 controls the wordline voltage generator circuit 300 so that the unit program time ismaintained at the reference value or decreased below the reference valuein accordance with the number of counted program data bits, counted bybit counter circuit 390 at each program loop including repeated programloops.

In one embodiment of the invention, the foregoing reference value forvoltage is a voltage that corresponds to a voltage required when the setof input data bits contains all program data bits, and the foregoingreference value for unit program time is a time that corresponds to theunit program time required when the set of input data bits contains allprogram data bits.

So, in flash memory device 300, according to one embodiment of theinvention, an initially determined configuration need not be maintaineduntil the program mode of operation is ended. Thus, repeated programloops may be executed with voltage increment sizes that are differentfrom the voltage increment size established in the initial program loop,or alternately, repeated program loops may be executed with unit programtimes that are different from the unit program time established in theinitial program loop.

In conclusion, it is possible to reduce programming time by variouslycontrolling either the increment size of the word line voltage or theunit program time in a given program loop in accordance with a number ofcounted program data bits.

The invention has been described using exemplary embodiments; however,the scope of the invention is not limited to the disclosed embodiments.Rather, it is intended to cover various modifications and similararrangements. The scope of the claims, therefore, should be accorded thebroadest interpretation so as to encompass all such modifications andsimilar arrangements.

1. A flash memory device, comprising: a word line voltage generatorcircuit configured to generate a word line voltage, wherein the wordline voltage is varied in accordance with an increment size; and, aprogram controller circuit adapted to control the word line voltagegenerator circuit and further adapted to define the increment size inaccordance with a number of program data bits in a set of input databits.
 2. The flash memory device of claim 1, wherein the programcontroller circuit executes a program loop comprising a program intervaland a program verify interval; and, wherein the increment size remainsconstant throughout the program interval.
 3. The flash memory device ofclaim 2, further comprising: a bit counter circuit configured to providea first count to the program controller circuit, wherein the first countcorresponds to the number of program data bits in the set of input databits.
 4. The flash memory device of claim 3, further comprising: aplurality of memory cells; a sense amplifier circuit configured to sensea plurality of data states from the plurality of memory cells; apass/fail check circuit configured to receive the plurality of datastates from the sense amplifier circuit, provide the plurality of datastates to the bit counter circuit, determine a judgment result from theplurality of data states, and provide the judgment result to the programcontroller circuit.
 5. The flash memory device of claim 4, wherein theprogram controller circuit is further adapted to control the bit countercircuit to provide a second count to the program controller circuit,wherein the second count corresponds to the number of program data bitsin the plurality of data states received from the pass/fail checkcircuit in relation to the program verify interval of the program loop.6. The flash memory device of claim 5, wherein the program controllercircuit executes a next program loop in accordance with the judgmentresult.
 7. A flash memory device, comprising: a word line voltagegenerator circuit configured to generate a word line voltage, whereinthe word line voltage is varied in accordance with an increment size;and, a program controller circuit adapted to control the word linevoltage generator circuit and further adapted to define a unit programtime for the word line voltage in accordance with a number of programdata bits in a set of input data bits.
 8. The flash memory device ofclaim 7, wherein the program controller circuit executes a program loopcomprising a program interval and a program verify interval; and,wherein the unit program time remains constant throughout the programinterval.
 9. The flash memory device of claim 8, further comprising: abit counter circuit configured to provide a first count to the programcontroller circuit, wherein the first count corresponds to the number ofprogram data bits in the set of input data bits.
 10. The flash memorydevice of claim 9, further comprising: a plurality of memory cells; asense amplifier circuit configured to sense a plurality of data statesfrom the plurality of memory cells; a pass/fail check circuit configuredto receive the plurality of data states from the sense amplifiercircuit, provide the plurality of data states to the bit countercircuit, determine a judgment result from the plurality of data states,and provide the judgment result to the program controller circuit. 11.The flash memory device of claim 10, wherein the program controllercircuit is further adapted to control the bit counter circuit to providea second count to the program controller circuit, wherein the secondcount corresponds to the number of program data bits in the plurality ofdata states received from the pass/fail check circuit in relation to theprogram verify interval.
 12. The flash memory device of claim 11,wherein the program controller circuit executes a next program loop inaccordance with the judgment result.
 13. A method for controlling aflash memory device, comprising: generating a word line voltage, whereinthe word line voltage is varied in accordance with an increment size;and, defining the increment size in accordance with a number of programdata bits in a set of input data bits.
 14. The method of claim 13,further comprising: maintaining the increment size at a constant sizethroughout a program interval of a program loop, the program loopcomprising the program interval and a program verify interval.
 15. Themethod of claim 14, further comprising: counting the number of programdata bits in the set of input data bits; and, storing the set of inputdata bits in a plurality of memory cells.
 16. The method of claim 15,further comprising: sensing a plurality of data states from theplurality of memory cells and providing the plurality of data states toa pass/fail check circuit; determining a judgment result based on theplurality of data states in the pass/fail check circuit and providingthe judgment result to a program controller circuit; and, providing theplurality of data states to a bit counter circuit.
 17. The method ofclaim 16, further comprising: counting the number of program data bitsin the plurality of data states received from the pass/fail checkcircuit in relation to the program verify interval; and, providing thecounted number of program data bits to the program controller circuit.18. The method of claim 17, further comprising: controlling a nextprogram loop in accordance with the judgment result and the countednumber of program data bits.
 19. A method for controlling a flash memorydevice, comprising: generating a word line voltage, wherein the wordline voltage is varied in accordance with an increment size; and,defining a unit program time for the word line voltage in accordancewith a number of program data bits in a set of input data bits.
 20. Themethod of claim 19, further comprising: maintaining the unit programtime constant throughout a program interval of a program loop, theprogram loop comprising the program interval and a program verifyinterval.
 21. The method of claim 20, further comprising: counting thenumber of program data bits in the set of input data bits; and, storingthe set of input data bits in a plurality of memory cells.
 22. Themethod of claim 21, further comprising: sensing a plurality of datastates from the plurality of memory cells and providing the plurality ofdata states to a pass/fail check circuit; determining a judgment resultbased on the plurality of data states in the pass/fail check circuit andproviding the judgment result to a program controller circuit; and,providing the plurality of data states to a bit counter circuit.
 23. Themethod of claim 22, further comprising: counting the number of programdata bits in the plurality of data states received from the pass/failcheck circuit in relation to the program verify interval; and, providingthe counted number of program data bits to the program controllercircuit.
 24. The method of claim 23, further comprising: controlling anext program loop in accordance with the judgment result and the countednumber of program data bits.